1. Field of the Invention
This invention relates to phase-locked loop (PLL) circuits, and, more particularly, to a circuit used in conjunction with an active loop filter to set the frequency of the voltage controlled oscillator to a predetermined frequency under abnormal operating conditions.
2. Background Description
A standard phase-lock loop comprises a phase detector, a loop-filter and a voltage controlled oscillator with a feedback circuit connected from the output of the voltage controlled oscillator (VCO) to the input of the phase detector. A reference frequency is applied to a second input to the phase detector and the output of the VCO is compared with this reference frequency to obtain an error signal which passes through the loop filter and then is applied as the control voltage to the control input of the VCO. The loop filter may be either passive or active; and, where an active filter is employed, it may provide an output signal which is either of two extreme levels, causing the VCO frequency to shift to its maximum or minimum operational frequency, when there is a loss of reference frequency. Such a condition also may be effected during alarm conditions from other elements of a system in which the phase lock loop is only a part. The loss of the reference frequency or an alarm condition would be considered as abnormal conditions, and when the loss of input or the presence of an alarm condition is removed, and the appropriate reference frequency is again applied to the phase detector, it is desirable that phase-locking should be acquired in the minimum possible time. Most often such a result may be obtained where the output of the voltage controlled oscillator has been forced to a frequency which is quite close to its normal operating frequency. Quite often this normal operating frequency is the nominal (or center) frequency of the VCO.
One technique for accomplishing such a result is disclosed in U.S. Pat. No. 3,882,412; "Drift Compensated Phase Lock Loop," by Garrett Gordon Apple, Jr. In the phase lock loop circuit of the referenced patent, a compensation means is disposed between the loop filter and the voltage control oscillator and a control means is disposed between the input to the phase lock loop and an input to the compensation means. The control means include a signal presence monitor, which simply determines whether or not the input signal to the phase lock loop is present. Further, it includes a very low frequency clock source, i.e., one pulse per hour or even per day, and an AND-gate which AND's the output of the signal presence monitor and the low frequency clock to provide an output clock signal to an up/down N-BIT counter which is included in the compensation means. Disadvantages of the disclosed technique are (1) the complexity of the circuit arrangement used, and (2) the operating delay which may permit the control voltage to be shifted off frequency prior to the time that the output voltage would have been locked to a particular value upon loss of the input signal.